Hardwired control versus
Microprogrammed control

There is no intrinsic difference:

Hardwired control is a control mechanism that generates control signals by using an appropriate finite state machine (FSM). Microprogrammed control is a control mechanism that generates control signals by reading a memory called a control storage (CS) that contains control signals. Although microprogrammed control seems to be advantageous to implement CISC machines, since CISC requires systematic development of sophisticated control signals, there is no intrinsic difference between these 2 types of control.

The pair of a "microinstruction-register" and a "control storage address register" can be regarded as a "state register" for hardwired control. Note that a control storage can be regarded as a combinational logic circuit. We can assign any 0,1 values to each output corresponding to each address, that can be regarded as the input for a combinational logic circuit. This is a truth table.

CISC also can be implemented by using hardwired control:

In the above sense, microprogrammed control is not always necessary to implement CISC machines. Hardwired control also can be used for implementing sophisticated CISC machines. The bases of this opinion are as follows:

  1. The same field configuration (state assignment) can be used for both of these two types of control. This is clear because of the above identification.

  2. We can use any large FSM, that has horizontal microcode like state assignment, since the delay for the FSM does not matter at all so long as it is less than or equal to the delay for the data-path that includes adders, shifters and so on, since the FSM works in parallel with the data-path.

  3. The horizontal microcode like state assignment has become very easy to be implemented because of the spread of the hardware description language (HDL). In Verilog HDL, g`defineh statements enable us to get perfect net-list for any large FSMs in a very short time by using appropriate logic synthesizers. "Parameter" statements also can be used for the state assignment in Verilog HDL.
CISCs and RISCs are two major different types of ordinary SISD machines. Since hardwired control has been historically faster, both of these two types of machines are implemented by using hardwired control in our microcomputer design educational environment City-1.

In 1996, that was the first year of City-1, an example description named CISC-1 with an FSM that uses a horizontal microcode like state assignment was given to all of junior students of the Department of Computer Engineering, Faculty of Information Sciences, Hiroshima City University. They succeeded.

Download descriptions in Verilog HDL

We decided to call digital systems with an FSM that generates horizontal microcode a "hardwired microcode machine (HM^2)."

Here we consider only horizontal type microprogrammed control. Vertical type has shorter formats as microprogrammed control, which must be decoded and interpreted by using more than a single clock cycle.


Related publications:

  1. Ryuichi TAKAHASHI: "System Development and Design Using Verilog HDL" Kyoritu-pub.(2008)ISBN978-4-320-12222-2...in Japanese

    ...HM^2 is clearly described in this book.

  2. Ryuichi TAKAHASHI, Kenta KANDA, Yuji KIHARA, Hajime OHIWA: "CS Education for High School Students Focusing on Energy Consumption on FPGA," Supplementary Proc. ICCE2007:15th International Conference on Computers in Education pp.39-40 (2007)

    ...We called the machine "hardwired microcode machine(HM^2)" for the first time in this paper. HM^2 contains an FSM that generates horizontal microcode.

  3. Ryuichi TAKAHASHI and Noriyoshi YOSHIDA: "Diagonal Examples for Design Space Exploration in an Educational Environment CITY-1," IEEE Proc. MSE 1999: International Conference on Microelectronic Systems Education, pp.71-73 (1999)...ACM, IEEE

    ...The second English paper introducing horizontal microcode like state assignment for an FSM.

  4. Ryuichi TAKAHASHI and Takeshi YOSHIMURA: "Strategies for High Level Synthesis" The Trans. of the IEICE, VolJ74-A, No.2, pp.143-151 (1991)...in Japanese

    ...The above idea is described also in this paper.

  5. Ryuichi TAKAHASHI, Takeshi YOSHIMURA and Satoshi GOTO: "A VLSI Architecture Evaluation System," ACM, IEEE Proc. ICCD 1986 :International Conference on Computer Design, pp.60-63 (1986)

    ...This is the first paper that illustrates the above identification, where the idea was used for quick quantitative evaluation of hardware resources. Although I had been working for NEC Corp., I didn't write any patent on this idea. Hardwired microcode machines are free to use.

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